View CXD2463_101573.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXD2463R
Timing Controller for CCD Camera
Description The CXD2463R generates the sync signals for timing control and back end signal processing in a CCD camera system using a 510H or 760H blackand-white CCD image sensor. Features * Built-in sync signal generation function * Built-in electronic iris (electronic shutter) function * Supports low-speed limiter for electronic iris * Supports external synchronization (Line-Lock, VReset + HPLL) * Supports automatic external sync discrimination * Window pulse output for backlight compensation * Built-in V driver Applications * Surveillance camera * Door phone camera Structure Silicon gate CMOS IC Applicable CCD Image Sensors * Type 1/2, 760H black-and-white CCD (EIA/CCIR) * Type 1/3, 510/760H black-and-white CCD (EIA/CCIR) * Type 1/4, 510/760H black-and-white CCD (EIA/CCIR) 48 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage VDD, AVDD VSS - 0.5 to VSS + 7.0 * Supply voltage VSS VL - 0.5 to VL + 26.0 * Supply voltage VH VL - 0.5 to VL + 26.0 * Supply voltage VM VL - 0.5 to VL + 26.0 * Input voltage VI VSS - 0.5 to VDD + 0.5 * Output voltage VO * Operating temperature Topr * Storage temperature Tstg VSS - 0.5 to VDD + 0.5 -20 to +75 -55 to +150
V V V V V V C C
Recommended Operating Conditions * Supply voltage 1 VDD, AVDD 4.75 to 5.25 * Supply voltage 3 VH 14.55 to 15.45 * Supply voltage 4 VL -9.0 to -8.0 * Supply voltage 5 VM 0 * Operating temperature Topr -20 to +75 Base oscillation * 1212fH (EIA: 19.0699MHz) (CCIR: 18.9375MHz) * 1820fH (EIA: 28.6364MHz) * 1816fH (CCIR: 28.375MHz)
V V V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E98930B9X
Block Diagram
VSS2 EVD EHD/SYNC EXT HVDET VD HD EIA VDD1 VDD2 VSS1 TEST 22 29 RST RESET GEN 21 ESHUT1 IVD EIA COUNTER DECODER 20 ESHUT2
39 37 SYNC DISCRIMINATION CIRCUIT 38 34 33 35 36 27 19 43 16 32
COMP
NO SIGNAL DETECTION CIRCUIT TEST CIRCUIT
LCIN 40 SYNC SEP VD HD
VD DETECTION CIRCUIT
LCOUT 41
HV-PLL SELECTOR
CKI 42 IRIS/SHUTTER CK GEN
HV-PLL SELECTOR GATE
1/2 IHD 1/525 1/625
CCD 28
1/606 1/910 1/908
AVSS 47
H1 45
H2 46
VL
8
VM
1
SUB
7 25 26 23 24 15 17 18 14 12 13 11 10 9
5
VH
V DRIVER
BLC
CVSS
Vreg
CLP1
SYNC
CBLK
CLP2
BLCW1
BLCW2
IRIN/ED1
CVDD
SPDNV/ED2
SPUPV/ED0
-2-
TG/SSG UP/DOWN ADDER
AVDD 44
GATE
RG 48
SHP 31
SELECTOR
SHD 30
V1
6 DECODE
V2
3
V3
4
V4
2
CXD2463R
CXD2463R
Pin Configuration (Top View)
HVDET EXT HD VD SYNC 25 24 CLP2 23 CLP1 22 TEST 21 ESHUT1 20 ESHUT2 19 VDD1 18 BLCW2 17 BLCW1 16 VSS1 15 BLC 14 CVSS 13 IRIN/ED1 1 VM 2 V4 3 V2 4 V3 5 VH 6 V1 7 SUB 8 VL 9 CVDD 10 Vreg 11 SPUPV/ED0 12 SPDNV/ED2 CBLK 26 VSS2 CCD 28 SHD SHP RST EIA 27
36 EVD EHD/SYNC COMP LCIN LCOUT CKI VDD2 AVDD H1 H2 AVSS RG 37 38 39 40 41 42 43 44 45 46 47 48
35
34
33
32
31
30
29
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VM V4 V2 V3 VH V1 SUB VL CVDD Vreg SPUPV/ED0 SPDNV/ED2 IRIN/ED1 CVSS I/O -- O O O -- O O -- -- -- I I I -- Power supply (GND for V driver) Pulse output for CCD vertical register drive Pulse output for CCD vertical register drive Pulse output for CCD vertical register drive Power supply (positive power supply for V driver) Pulse output for CCD vertical register drive CCD discharge pulse output Power supply (negative power supply for V driver) Power supply (for comparator) Bias current supply for comparator Shutter speed up reference voltage/shutter speed setting Shutter speed down reference voltage/shutter speed setting Iris signal input/shutter speed setting GND (for comparator) -3- Description
CXD2463R
Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Symbol BLC VSS1 BLCW1 BLCW2 VDD1 ESHUT2 ESHUT1 TEST CLP1 CLP2 SYNC CBLK EIA CCD RST SHD SHP VSS2 HVDET EXT VD HD EVD EHD/SYNC COMP LCIN LCOUT CKI VDD2 AVDD H1 H2 AVSS RG
I/O O -- I I -- I I I O O O O I I I O O -- O O O O I I O I O I -- -- O O -- O
Description Window pulse output for backlight compensation GND Window select 1 for backlight compensation (with pull-down resistor) Window select 2 for backlight compensation (with pull-down resistor) Power supply Sub pulse control (with pull-down resistor) Sub pulse control (with pull-down resistor) Fixed low (with pull-down resistor) Clamp pulse output Clamp pulse output Composite sync output Composite blanking output Low: EIA, High: CCIR (with pull-down resistor) Low: 510H, High: 760H (with pull-down resistor) Reset (low reset). Always input reset pulse after power-on. Data sample-and-hold pulse Precharge level sample-and-hold pulse GND Horizontal PLL/Vertical PLL discrimination signal High: Vertical PLL, Low: Horizontal PLL External sync/internal sync discrimination signal High: External sync, Low: Internal sync Vertical drive output Horizontal drive output Vertical drive signal input (with pull-up resistor) Horizontal drive signal input/Composite sync input (with pull-up resistor) Comparator output Inverter input for oscillation Inverter output for oscillation 2MCK input Power supply Power supply (for H1, H2, and RG) H1 clock output for CCD horizontal register drive H2 clock output for CCD horizontal register drive GND (for H1, H2, and RG) Reset gate pulse output -4-
CXD2463R
Electrical Characteristics 1) DC Characteristics Item Supply voltage Input voltage 1 (For input pins not listed below) Input voltage 2 (Pin 29) Input voltage 3 (Pins 11 and 12 in electronic iris mode) Input voltage 4 (Pin 13 in electronic iris mode) Symbol VDD VIH1 VIL1 VIH2 VIL2 VIN3 2.0 0.8VDD 0.2VDD VDD Conditions (VDD = 5V 0.25V, Topr = -20 to +75C) Min. 4.75 0.7VDD 0.3VDD Typ. 5.0 Max. 5.25 Unit V V V V V V
VIN4 IOH = -4.0mA IOL = 8.0mA IOH = -6.9mA IOL = 3.0mA IOH = -17.4mA IOL = 12.0mA IOH = -6.0mA IOL = 4.0mA IOH = -5.0mA IOL = 10.0mA IOH = -7.2mA IOL = 5.0mA IOH = -4.0mA IOL = 5.4mA VIN = VDD or VSS VIN = VDD or VSS VIL = 0V VIH = VDD AVDD = 5V CVDD = 5V VDD1 = 5V VDD2 = 5V VL = -8.5V VH = 15V -5-
VSS VDD - 0.8
VDD
V V
VOH1 Output voltage 1 (Pins 15, 23, 24, 25, 26, 33, 34, 35 and 36) VOL1 Output voltage 2 (Pins 30, 31 and 48) Output voltage 3 (Pins 45 and 46) Output voltage 4 (Pin 39) Output voltage 5 (Pins 2, 3, 4 and 6) Output voltage 6 (Pins 4 and 6 (SG)) Output voltage 7 (Pin 7) Feedback resistor 1 (Pin 42) Feedback resistor 2 (Resistor between Pins 40 and 41) Pull-up resistor Pull-down resistor VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 RFE1 RFE2 RPU RRD IVM Current consumption IVL IVH
0.4 VDD - 0.8 0.4 VDD - 0.8 0.4 VDD - 0.8 0.4 VM - 0.25 VL + 0.25 VH - 0.25 VM + 0.25 VH - 0.25 VL + 0.25 250k 250k 20k 20k 1M 1M 50k 50k 24 2.5M 2.5M 125k 125k
V V V V V V V V V V V V V mA
1.9 0.8
mA mA
The typical power consumption is 148mW with the ICX054BL load (in the normal operating state).
CXD2463R
2) Input/Output Capacitance Item Input pin capacitance Output pin capacitance I/O pin capacitance Symbol CIN COUT CI/O Min.
(VDD = VI = 0V, fM = 1MHz) Typ. Max. 9 11 11 Unit pF pF pF
3) Comparator Characteristics (VDD = 5V 0.25V, Topr = -20 to +75C) Item Indefinite region Symbol Vf Min. Typ. Max. 70 Unit mV
Note 1) Input offset voltage and indefinite region The input offset voltage and indefinite region (region in which the comparator output is not set to high or low) shown in the figure below exist in the built-in comparator in this IC, so be careful when designing the external circuit. Note 2) Pins 11 and 12 in electronic iris mode Make sure of Pin 11 (SPUPV) < Pin 12 (SPDNV).
5.0V
70mV 70mV
Pins 11 and 12 (SPUPV, SPDNV)
Indefinite region GND
4) Power-on Reset Condition
4.75V VDD
RST 0.2VDD tWRST
(Within the recommended operating condition) Item Power-on reset period Symbol Min. 35 -6- Typ. Max. Unit ns
tWRST
CXD2463R
1. Electronic Iris/Electronic Shutter Function The electronic iris or electronic shutter can be selected by setting the following pins to different combinations of high and low. ESHUT1 Pin 21 L H L H ESHUT2 Pin 20 L L H H Operating Mode Electronic iris without limiter Electronic iris with limiter EIA: 1/100 (s), CCIR: 1/120 (s) Electronic shutter mode Sub pulse stopped
1) Electronic Iris Mode Symbol IRIN/ED1 SPDNV/ED2 SPUPV/ED0 Pin No. 13 12 11 Iris signal input Shutter speed down reference voltage Shutter speed up reference voltage Function
2) Electronic Shutter Mode Symbol SPUPV/ED0 IRIN/ED1 SPDNV/ED2 Pin No. 11 13 12 H H H EIA: 1/100 CCIR: 1/120 L H H H L H L L H Mode H H L L H L H L L L L L
Shutter speed
1/250
1/500
1/1000
1/2000
1/5000 1/10000 1/100000
-7-
CXD2463R
2. Backlighting Correction Function The CXD2463R has a function to output the window pulse for backlight compensation. The backlight compensation pulse is output from BLC (Pin 15) in the following range according to the high/low combination of BLCW1 (Pin 17) and BLCW2 (Pin 18). Window Type for Different Pin Combinations Window type Full-screen photometry Bottom emphasis photometry Center emphasis photometry Bottom + center emphasis photometry BLCW1 (Pin 17) BLCW2 (Pin 18) L H L H L L H H
Example of Basic Circuit Configuration
+5V 39k 10 10k 27 IRIS
Iris comparator 13 IRIN/ED1
Iris window switch 3.9k 10k
10k
100k
10
19 OP+ 13 DETOUT BLC 15 AGC window switch 10k 1k
100k CXD2463R CXA1310AQ
Full-screen photometry
Bottom emphasis photometry
Center emphasis photometry
Bottom + center emphasis photometry
-8-
CXD2463R
1) Window Pulse Timing Charts * EIA Mode/Vertical Direction Timing (1) Full-screen photometry
VD
HD
0.5HD BLC 20HD 20.5HD
(2) Center emphasis photometry
VD
HD
101HD BLC 181HD
101.5HD 181.5HD
(3) Bottom emphasis photometry
VD
HD
0.5HD BLC 181HD 181.5HD
-9-
CXD2463R
* EIA Mode/Horizontal Direction Timing (1) Bottom emphasis photometry and full-screen photometry
HD
MCK
BLC
X1
X2
510H X1 760H 510H X2 760H
104MCK 154MCK 3MCK 22MCK
(2) Center emphasis photometry
HD
MCK
BLC
X1
X2
X1
510H 760H 510H 760H
272MCK 407MCK 167MCK 252MCK
X2
- 10 -
CXD2463R
* CCIR Mode/Vertical Direction Timing (1) Full-screen photometry
VD
HD
0.5HD BLC 25HD 25.5HD
(2) Center emphasis photometry
VD
HD
121HD BLC 216HD
121.5HD 216.5HD
(3) Bottom emphasis photometry
VD
HD
0.5HD BLC 216HD 216.5HD
- 11 -
CXD2463R
* CCIR Mode/Horizontal Direction Timing (1) Bottom emphasis photometry and full-screen photometry
HD
MCK
BLC
X1
X2
X1
510H 760H 510H 760H
114MCK 169MCK 3MCK 22MCK
X2
(2) Center emphasis photometry
HD
MCK
BLC
X1
X2
X1
510H 760H 510H 760H
279MCK 416MCK 164MCK 246MCK
X2
- 12 -
CXD2463R
3. External Sync Function The CXD2463R supports the three modes of Line-Lock, VReset + HPLL (VD and HD inputs), and VReset + HPLL (Sync input) as the external sync functions. Each mode is automatically switched according to the combination of signals input to EHD/SYNC (Pin 38) and EVD (Pin 37). 1) Automatic External Sync Discrimination I/O I I O O Symbol EHD/SYNC EVD HVDET EXT Mode Pin No. 38 37 33 34 HD No signal L L INT EHD/SYNC and EVD pins signal input state and HVDET and EXT pins discrimination results No signal VD H H LL HD VD L H VReset + HPLL SYNC HD after SYNC separation L H VReset + HPLL No signal No signal L L INT
* If unspecified signals are input for the external signals given above, there may be recognition errors. 2) LL (Line-Lock) Mode When the V sync clock is externally input to EVD (Pin 37), the result of comparing the falling edge of the clock and the falling edge of the internal VD is output from COMP (Pin 39). The output polarity is compatible with the active filter.
EXT-VD (Pin 37)
INT-VD (Pin 35)
COMP (Pin 39)
High impedance state
- 13 -
CXD2463R
3) VReset + HPLL (VD and HD Inputs) Mode When the HD cycle clock is externally input to EHD/SYNC (Pin 38) and the V cycle clock is externally input to the EVD (Pin 37), the CXD2463R sync signal is output as shown below based on the phase difference between these signals. Similar to Line-Lock mode, the result of comparing the phase of the falling edges of the HD cycle clock input to Pin 38 and the CXD2463R internal HD is output from COMP (Pin 39). The PLL is applied using this signal. Similar to Line-Lock mode, the polarity of the COMP (Pin 39) output is compatible with the active filter. The phase of the HD falling edge can be shifted up to 1/4H with respect to the falling edge of the master VD (EXTVD). * EIA/ODD (1) EXT-VD and EXT-HD have the same phase.
1/4H 1/4H
EXT-VD (Pin 37 input) EXT-HD (Pin 38 input) VD (Pin 35 output) HD (Pin 36 output) SYNC (Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD EXT-HD VD HD SYNC
(3) EXT-VD and EXT-HD have the -1/4H to the same phase.
EXT-VD EXT-HD VD HD SYNC
- 14 -
CXD2463R
* EIA/EVEN (1) EXT-VD and EXT-HD have the same phase.
1/4H 1/4H
EXT-VD (Pin 37 input) EXT-HD (Pin 38 input) VD (Pin 35 output) HD (Pin 36 output) SYNC (Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD EXT-HD VD HD SYNC
(3) EXT-VD and EXT-HD have the same phase to -1/4H.
EXT-VD EXT-HD VD HD SYNC
- 15 -
CXD2463R
* CCIR/ODD (1) EXT-VD and EXT-HD have the same phase.
1/4H 1/4H
EXT-VD (Pin 37 input) EXT-HD (Pin 38 input) VD (Pin 35 output) HD (Pin 36 output) SYNC (Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD EXT-HD VD HD SYNC
(3) EXT-VD and EXT-HD have the same phase to -1/4H.
EXT-VD EXT-HD VD HD SYNC
- 16 -
CXD2463R
* CCIR/EVEN (1) EXT-VD and EXT-HD have the same phase.
1/4H 1/4H
EXT-VD (Pin 37 input) EXT-HD (Pin 38 input) VD (Pin 35 output) HD (Pin 36 output) SYNC (Pin 25 output)
(2) EXT-VD and EXT-HD have the same phase to +1/4H.
EXT-VD EXT-HD VD HD SYNC
(3) EXT-VD and EXT-HD have the same phase to -1/4H.
EXT-VD EXT-HD VD HD SYNC
- 17 -
CXD2463R
4) VReset + HPLL (SYNC Input) Mode When the specified sync signal is externally input to EHD/SYNC (Pin 38), the EXT-HD separated from this sync signal is output from HD (Pin 36). This signal is input through the shifter to EVD (Pin 37). At this time, the CXD2463R sync signal is output as shown below based on the amount by which EXT-HD is shifted. (The phase can be shifted up to 1/2H with respect to the falling edge of EXT-HD.) COMP (Pin 39) outputs the result of comparing the phase of the falling edge of the shifted EXT-HD (signal input to Pin 37) and the falling edge of the CXD2463R internal HD. The polarity is compatible with the active filter. * EIA/ODD
1/2H 1/2H
EXT-SYNC (Pin 38 input) EXT-VD (Generated inside the CXD2463R) EXT-HD (Pin 36 output) (1) Same phase SFT-HD (1) (Pin 37 input) VD (Pin 35 output) HD (Generated inside the CXD2463R) SYNC (Pin 25 output)
(2) Delayed phase SFT-HD (2) VD HD SYNC
(3) Advanced phase SFT-HD (3) VD HD SYNC SFT-HD (1) to (3) are the signals after shifting EXT-HD.
- 18 -
CXD2463R
* EIA/EVEN
1/2H 1/2H
EXT-SYNC (Pin 38 input) EXT-VD (Generated inside the CXD2463R) EXT-HD (Pin 36 output) (1) Same phase SFT-HD (1) (Pin 37 input) VD (Pin 35 output) HD (Generated inside the CXD2463R) SYNC (Pin 25 output)
(2) Delayed phase SFT-HD (2) VD HD SYNC
(3) Advanced phase SFT-HD (3) VD HD SYNC
- 19 -
CXD2463R
* CCIR/ODD
1/2H 1/2H
EXT-SYNC (Pin 38 input) EXT-VD (Generated inside the CXD2463R) EXT-HD (Pin 36 output) (1) Same phase SFT-HD (1) (Pin 37 input) VD (Pin 35 output) HD (Generated inside the CXD2463R) SYNC (Pin 25 output)
(2) Delayed phase SFT-HD (2) VD HD SYNC
(3) Advanced phase SFT-HD (3) VD HD SYNC
- 20 -
CXD2463R
* CCIR/EVEN
1/2H 1/2H
EXT-SYNC (Pin 38 input) EXT-VD (Generated inside the CXD2463R) EXT-HD (Pin 36 output) (1) Same phase SFT-HD (1) (Pin 37 input) VD (Pin 35 output) HD (Generated inside the CXD2463R) SYNC (Pin 25 output)
(2) Delayed phase SFT-HD (2) VD HD SYNC
(3) Advanced phase SFT-HD (3) VD HD SYNC
- 21 -
Timing Generator + Sync Generator Block Timing Chart Vertical Direction EIA (during 510H/760H CCD drive)
FIELD.E
FIELD.O
HD
VD
20H
9H
SYNC
BLK
V1
V2
V3
V4
2 1
491
510H CCD OUT
3 2 3
493
492
760H CCD OUT
1
493
494
CLP1
- 22 -
9H 20H
1 2 1 2 3 4 3 4
CLP2
FIELD.O
FIELD.E
HD
VD
SYNC
BLK
V1
V2
V3
V4
510H CCD OUT
492
760H CCD OUT
493 492 494
493
CXD2463R
CLP1
CLP2
Timing Generator + Sync Generator Block Timing Chart Vertical Direction CCIR (during 510H CCD drive)
FIELD.E
FIELD.O
HD
VD
25H
7.5H
SYNC
BLK
V1
V2
V3
V4
2 1 3
581
510H CCD OUT
583
582
CLP1
CLP2
- 23 -
25H
1 2 3 4
FIELD.O FIELD.E
HD
VD
7.5H
SYNC
BLK
V1
V2
V3
V4
510H CCD OUT
582
583
CLP1 CXD2463R
CLP2
Timing Generator + Sync Generator Block Timing Chart Vertical Direction CCIR (during 760H CCD drive)
FIELD.E
FIELD.O
HD
VD
25H
7.5H
SYNC
BLK
V1
V2
V3
V4
2 1 3
760H CCD OUT
581 583
582
CLP1
- 24 -
25H
1 2
CLP2
FIELD.O FIELD.E
HD
VD
7.5H
SYNC
BLK
V1
V2
V3
V4
760H CCD OUT
582
583
CLP1 CXD2463R
CLP2
Timing Generator + Sync Generator Block Timing Chart Horizontal Direction EIA (during 510H CCD drive)
MCK = 104.88ns 20
59 104
0
10
30
40
50
60
70
80
90
100
110
HD/BLK
MCK (Internal clock)
26 79
H1
H2
RG
SHP
SHD
23 80 32 44 26 38 55 14 14 14 36 59 56 68 72 62 50 94
CLP1
7
- 25 -
CLP2
V1
V2
V3
V4
SUB
HSYNC
EQ
VSYNC
VD CXD2463R
Timing Generator + Sync Generator Block Timing Chart Horizontal Direction CCIR (during 510H CCD drive)
MCK = 105.61ns 20
59
0
10
30
40
50
60
70
80
90
100
110
114
HD/BLK
MCK (Internal clock)
31 84
H1
H2
RG
SHP
SHD
23 85 37 49 31 43 60 59 36 61 73 77 67 55 99
CLP1
7
- 26 -
CLP2
V1
V2
V3
V4
SUB
HSYNC
14
EQ
14
VSYNC
14
VD CXD2463R
Timing Generator + Sync Generator Block Timing Chart Horizontal Direction EIA (during 760H CCD drive)
MCK = 69.84ns 60
90 154
0
10
20
30
40
50
70
80
90
100
110
120
130
140
150
160
170
HD/BLK
MCK (Internal clock)
40 118
H1
H2
RG
SHP
SHD
36 119 49 67 40 58 85 90 56 85 103 108 94 76 140
CLP1
12
- 27 -
CLP2
V1
V2
V3
V4
SUB
HSYNC
22
EQ
22
VSYNC
22
CXD2463R
VD
Timing Generator + Sync Generator Block Timing Chart Horizontal Direction CCIR (during 760H CCD drive)
MCK = 70.48ns 30
90
0
10
20
40
50
60
70
80
90
100
110
120
130
140
150
160
170
169
HD/BLK
MCK (Internal clock)
40 132
H1
H2
RG
SHP
SHD
36 133 51 73 40 62 95 90 56 95 117 122 84 106 154
- 28 -
CLP1
12
CLP2
V1
V2
V3
V4
SUB
HSYNC
22
EQ
22
VSYNC
22
CXD2463R
VD
Timing Generator + Sync Generator Block Timing Chart Charge Readout Timing Field Accumulation (during 510H CCD drive)
E: 2.51s (24CK) C: 2.53s E: EIA 1CK = 104.88ns C: CCIR 1CK = 105.61ns
HD (12CK) E: 1.26s C: 1.27s E: 1.57s (15CK) C: 1.58s
E: 38.38s (366CK) C: 38.65s
ODD
V1
V2
V3
- 29 -
(3CK) E: 0.32s C: 0.32s
V4
EVEN
E: 1.99s (19CK) C: 2.00s
V1
V2
V3
V4 CXD2463R
Timing Generator + Sync Generator Block Timing Chart Charge Readout Timing Field Accumulation (during 760H CCD drive)
E: 2.51s (36CK) C: 2.54s E: EIA 1CK = 69.84ns C: CCIR 1CK = 70.48ns
HD (23CK) E: 1.61s C: 1.62s E: 2.51s (36CK) C: 2.54s
E: 40.56s (581CK) C: 40.95s
ODD
V1
V2
V3
- 30 -
(3CK) E: 0.21s C: 0.21s
V4
EVEN
E: 2.51s (36CK) C: 2.54s
V1
V2
V3
V4 CXD2463R
Timing Generator + Sync Generator Block Timing Chart Effective Horizontal Period (during 510H CCD drive)
EIA 31.78s (303CK) 1/2H
1CK = 104.88ns
1.47s (14CK) 6.19s (59CK)
HD
BLK (HD)
10.90s (104CK)
BLK (ODD)
BLK (EVEN)
- 31 -
1.47s (14CK) 4.72s (45CK) 2.30s (22CK)
VD (ODD)
VD (EVEN)
HSYNC
EQ
2.30s (22CK)
VSYNC
4.72s (45CK)
4.72s (45CK)
CXD2463R
Timing Generator + Sync Generator Block Timing Chart Effective Horizontal Period (during 510H CCD drive)
CCIR 32.00s (303CK) 1/2H
1CK = 105.61ns
1.48s (14CK) 6.23s (59CK)
HD
BLK (HD)
12.04s (114CK)
BLK (ODD)
BLK (EVEN)
- 32 -
1.48s (14CK) 4.75s (45CK) 2.30s (22CK)
VD (ODD)
VD (EVEN)
HSYNC
EQ
2.30s (22CK)
VSYNC
4.75s (45CK)
4.75s (45CK)
CXD2463R
Timing Generator + Sync Generator Block Timing Chart Effective Horizontal Period (during 760H CCD drive)
EIA 31.78s (455CK) 1/2H 1CK = 69.84ns
1.54s (22CK)
HD
6.29s (90CK)
BLK (HD)
10.76s (154CK)
BLK (ODD)
BLK (EVEN)
- 33 -
1.54s (22CK) 4.75s (68CK) 2.37s (34CK)
VD (ODD)
VD (EVEN)
HSYNC
EQ
2.37s (34CK)
VSYNC
4.75s (68CK)
4.75s (68CK)
CXD2463R
Timing Generator + Sync Generator Block Timing Chart Effective Horizontal Period (during 760H CCD drive)
CCIR 32.00s (454CK) 1/2H
1CK = 70.48ns
1.55s (22CK) 6.34s (90CK)
HD
BLK (HD)
11.91s (169CK)
BLK (ODD)
BLK (EVEN)
- 34 -
1.55s (22CK) 4.79s (68CK) 2.40s (34CK) 4.79s (68CK)
VD (ODD)
VD (EVEN)
HSYNC
EQ
2.40s (34CK)
VSYNC
4.79s (68CK)
CXD2463R
CXD2463R
High-Speed Phase Timing Chart for the Timing Generator Block
MCK (Internal clock)
H1
H2
RG
CCD OUT
SHP
SHD
- 35 -
Application Circuit
+5V Reset circuit H shifter
* SYNC input external synchronization * Electronic iris mode
SYNC IN
0.01 10k 36 35 34 33 32 31 30 29 28 27 26 25 100 10k 38 23 22 21 20 19 CXD2463R 18 17 16 15 14 13 1 3 4 5 6 7 8 2 9 10 11 12 10k 10k 100k 10 3.9k 10 39k 10k 100 39 40 41 1p 42 43 44 45 46 47 48 37 24 25 30 27
4 29 21 20 24
0.1
1M
100k
10k
1000p
10p
CXA1310AQ
1M
1000p
- 36 -
RG ADJ 36k 50k 50k VSUB ADJ 510H/760H black-and-white CCD
VIDEO OUT
-9.0 to -8.0V +14.55 to +15.45V
CCD OUT
CXD2463R
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXD2463R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
B
(0.22)
+ 0.05 0.127 - 0.02 0.13 M
0.1 0.1 0.1
0.5 0.2
S
(0.127) +0.05 0.127 - 0.02
(0.18)
0.18 0.03
0 to 10
0.5 0.2
DETAIL B:SOLDER DETAIL A
DETAIL B:PALLADIUM
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
- 37 -
0.127 0.04
+ 0.08 0.18 - 0.03

▲Up To Search▲

Price & Availability of CXD2463

	To Download CXD2463 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .